The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. Furthermore, all embodiments are not necessarily intended to solve all or even any of the problems brought forward in this section.
A System-on-Chip (SoC) platform typically comprises at least one embedded Central Processing Unit (CPU) or processor, at least one embedded functional unit (also called an IP in the jargon of the one with ordinary skills in the art) which may be a memory (for instance of the eSRAM type), a Memory Management Unit (MMU), and/or at least one register. The components of the SoC are typically interconnected through an internal bus matrix.
In operation, the SoC platform may be led to manipulate sensitive data, for instance, cryptographic secret keys or unencoded secret data like passwords. To prevent unauthorized access to and/or corruption of these sensitive data, the architecture of the SoC platform may be split into two physically and functionally separated environments: a secure environment for manipulating sensitive data and a public environment for processing non-sensitive data. The secure environment comprises notably one or more dedicated secure memories and/or one or more secure hardware registers to store sensitive data, whereas the public environment may include its own dedicated memories and/or hardware registers to store public data.
This separation is for example implemented by Advanced RISC Machine (ARM) SoC platforms with security extensions, for example the TrustZone™ technology. A clear frontier between these two environments may be implemented with hardware (HW) and/or software (SW) mechanisms embedded in the processor, in the bus matrix, and in the IPs themselves. This frontier ensures that secure data within the secure environment cannot be accessed by any public component belonging to the public environment. This may typically be the case for active modes of operation of the platform, wherein memories, IPs and processors are kept powered-on or in retention. However, some modes of operation are available wherein one or more of the secure components can be powered off, meaning that at least some of their contents have to be saved during the particular mode and be restored thereafter. Such modes may be available for the purpose of optimizing the power strategy of the chip and decrease energy leakages.
A dedicated persistent secure memory, included in the secure environment, may be used to store securely sensitive data present in the secure environment before switching from an active mode to an energy saving mode (low-power mode). Persistent memory may include ROM memories of any available types for instance.
The European patent application EP10191115 discloses a possible method to manage switching between the two modes of operation for a processing device comprising multiple cores and/or processors.
To enable a safe and efficient switching, communications can be established between cores and/or processors, typically in a “master-slave” communication architecture. The master-slave communications may imply that cores/processors have to be asleep or waken-up synchronously. In particular, it may be impossible to switch off/on only one of the cores/processors, while other ones are still active.
Moreover, one can design a processing architecture with, for instance, two multi-cores processors: one for high performances (such as video encoding), and another one for low consumption scenarios (such as global monitoring of inputs). In such architectures (also named “big-little” architecture), it may be advantageous to power-off the high-performance processor to save battery. Communications between processors can imply a lot of possible and complex use cases that are to be handled by the processors. Thus, developing codes for handling such use cases can be difficult and complex.
Embodiments of the present invention aim at simplifying the architecture and increasing the flexibility of frameworks during the management of low power modes.